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Integrated Circuit Systems, Inc.
ICS9248-107
Frequency Timing Generator for PENTIUM II Systems
Recommended Application: RCC chipset Output Features: * 4 - CPUs @ 2.5V, up to 180MHz. * 3 - IOAPIC @ 2.5V * 3 - 3V66MHz @ 3.3V. * 11 - PCIs @ 3.3V * 1 - 48MHz, @ 3.3V fixed * 1 - 24/48MHz, @ 3.3V Features: * Up to 180MHz frequency support * * * * * Use a zero delay buffer such as the ICS9179-06 to generate SDRAM clocks. Support power management: Power down Mode from I2C programming. Spread spectrum for EMI control 0.25% center spread). Uses external 14.318MHz crystal 5 - FS pins for frequency select
Pin Configuration
GNDREF REF0 *SEL24_48#/REF1 VDDREF X1 X2 GNDPCI *FS0/PCICLK_F *FS1/PCICLK1 VDDPCI *FS2/PCICLK2 *FS3/PCICLK3 GNDPCI PCICLK4 PCICLK5 VDDPCI PCICLK6 PCICLK7 GNDPCI PCICLK8 PCICLK9 PCICLK10 VDDPCI PD# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 VDDLAPIC IOAPIC0 IOAPIC1 GNDLAPIC IOAPIC2 VDDLCPU CPUCLK0 GNDLCPU CPUCLK1 VDDLCPU CPUCLK2 CPUCLK3 GNDLCPU VDD66 3V66_0 3V66_1 3V66_2 GND66 SDATA 2 IC SCLK
ICS9248-107
{
VDD48 48MHz/FS4* 24_48MHz GND48
48-pin SSOP
*120K ohm pull-up to VDD on indicated inputs.
Key Specifications: * CPU Output Jitter: <250ps * * * * * * * * * * IOAPIC Output Jitter: <500ps 48MHz, 3V66, PCI Output Jitter: <500ps Ref Output Jitter. <1000ps
PLL2
Block Diagram
48MHz /2 X1 X2 XTAL OSC PLL1 Spread Spectrum 24_48MHz
CPU Output Skew: <175ps IOAPIC Output Skew <250ps PCI Output Skew: <580ps 3V66 Output Skew <250ps CPU to 3V66 Output Offset: 0.8 - 1.8ns (typ = 1.3ns) CPU to PCI Output Offset: 0.0 - 1.5ns (typ = 1.0ns) CPU to IOAPIC Output Offset: 1.5 - 4.0ns (typ = 2.0ns)
SEL24_48# IC
2
REF(1:0)
CPU DIVDER
CPUCLK (3:0)
IOAPIC DIVDER
IOAPIC (2:0)
Control Logic Config. Reg.
{
PCI DIVDER
PCICLK (10:0) PCICLK_F
SDATA SCLK
FS(4:0) PD#
3V66 DIVDER
3V66 (2:0)
9248-107 RevA - 5/21/01
ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.
ICS9248-107
General Description
The ICS9248-107 is a main clock synthesizer chip for Pentium II based systems using Rambus Interface DRAMs. This chip provides all the clocks required for such a system when used with a zero delay buffer such as the ICS9179-06. Spread Spectrum may be enabled through I2C. Spread spectrum typically reduces system EMI by 8dB to 10dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9248-107 employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature variations.
Pin Descriptions
Pin number Pin name 1, 7, 13, 19, 25, 31 GND 2 REF0 REF1 3 SEL24_48# 4, 10, 16, 23, VDD 28, 35 5 X1 6 X2 PCICLK_F 8 FS0 PCICLK1 9 FS1 PCICLK2 11 FS2 PCICLK3 12 FS3 14, 15, 17, 18, 20, PCICLK (4:10) 21, 22 24 26 27 29 30 32, 33, 34 36, 41 37, 38, 40, 42 39, 43 45 44, 46, 47 48 PD# 24_48MHz 48MHz FS4 SCLK SDATA 3V66(2:0) GNDLCPU CPUCLK(3:0) VDDLCPU GNDLAPIC IOAPIC(2:0) VDDLAPIC Type PWR OUT OUT IN PWR IN OUT OUT IN OUT IN OUT IN OUT IN OUT IN OUT OUT IN IN I/O OUT PWR OUT PWR PWR OUT PWR Description Ground pins 14.318MHz reference clock outputs at 3.3V 14.318MHz reference clock outputs at 3.3V Logic input to select 24 or 48MHz for pin 26 output Power pins 3.3V XTAL_IN 14.318MHz crystal input XTAL_OUT Crystal output Free running PCI clock at 3.3V. Synchronous to CPU clocks. Logic - input for frequency selection PCI clock output at 3.3V. Synchronous to CPU clocks. Logic - input for frequency selection PCI clock output at 3.3V. Synchronous to CPU clocks. Logic - input for frequency selection PCI clock output at 3.3V. Synchronous to CPU clocks. Logic - input for frequency selection PCI clock outputs at 3.3V. Synchronous to CPU clocks. This asynchronous input powers down the chip when drive active(Low). The internal PLLs are disabled and all the output clocks are held at a Low state. 24 or 48MHz output selectable by SEL24_48# (0=48MHz 1=24MHz) Fixed 48MHz clock output at 3.3V Logic - input for frequency selection Clock input of I C input Data pin for I2C circuitry 5V tolerant 3.3V clock outputs. Ground pins for CPUCLKs Host bus clock output at 2.5V. Power pins for CPUCLKs. 2.5V Ground pin for the IOAPIC outputs. IOAPIC clocks at 2.5V. Synchronous with CPUCLKs. Power pin for the IOAPIC outputs. 2.5V.
2
2
ICS9248-107
Functionality
FS4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FS3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 FS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 FS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 FS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 CPU 103.0 100.0 100.5 100.9 107.1 109.0 112.0 114.0 116.0 118.0 133.3 120.0 122.0 125.0 50.0 66.7 133.3 133.9 138 142 146 150 153 156 159.1 162 166.7 168 171 174 177 180 PC I 34.33 33.33 33.48 33.63 35.70 36.33 37.33 28.50 29.00 29.50 33.33 30.00 30.50 31.25 16.67 16.67 33.33 33.48 34.5 35.5 36.5 37.5 38.25 39 39.78 40.5 41.67 42 42.75 43.5 44.25 45 3V66 68.67 66.67 66.97 67.27 71.40 72.67 74.67 57.00 58.00 59.00 66.65 60.00 61.00 62.50 33.33 33.33 66.67 66.95 69 71 73 75 76.5 78 79.55 81 83.33 84 85.5 87 88.5 90 IOAPIC 17.17 16.67 16.74 16.82 17.85 18.17 18.67 14.25 14.50 14.75 16.66 15.00 15.25 15.63 8.33 8.33 16.67 16.74 17.25 17.75 18.25 18.75 19.13 19.5 19.89 20.25 20.83 21 21.38 21.75 22.13 22.5
3
ICS9248-107
Serial Configuration Command Bitmap
Byte 0: Functionality and frequency select register (Default = 0)
Bit Bit 2 FS4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bit 7 FS3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Bit 6 FS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 Bit 5 FS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Description Bit 4 CPU FS0 0 103.0 1 100.0 0 100.45 1 100.9 0 107.1 1 109.0 0 112.0 1 114.00 0 116.00 1 118.00 0 133.30 1 120.00 0 122.00 1 125.00 0 50.0 1 66.7 0 133.3 1 133.9 0 138.0 1 142.0 0 146.0 1 150.0 0 153.0 1 156.0 0 159.1 1 162.0 0 166.7 1 168.0 0 171.0 1 174.0 0 177.0 1 180.0 PWD PCI 34.33 33.33 33.48 33.63 35.70 36.33 37.33 28.50 29.00 29.50 33.33 30.00 30.50 31.25 16.67 16.67 33.33 33.48 34.50 35.50 36.50 37.50 38.25 39.00 39.78 40.50 41.67 42.00 42.75 43.50 44.25 45.00 3V66 68.67 66.67 66.97 67.27 71.40 72.67 74.67 57.00 58.00 59.00 66.65 60.00 61.00 62.50 33.33 33.33 66.67 66.95 69.00 71.00 73.00 75.00 76.50 78.00 79.55 81.00 83.33 84.00 85.50 87.00 88.50 90.00 IOAPIC 17.17 16.67 16.74 16.82 17.85 18.17 18.67 14.25 14.50 14.75 16.66 15.00 15.25 15.63 8.33 8.33 16.67 16.74 17.25 17.75 18.25 18.75 19.13 19.50 19.89 20.25 20.83 21.00 21.38 21.75 22.13 22.50
Bit (2, 7:4)
00010 Note 1
Bit 3 Bit 1 Bit 0
0 - Frequency is selected by hardware select, latched inputs 1 - Frequency is selected by Bit 2, 7:4 0 - Normal 1 - Spread spectrum enabled 0 - Running 1 - Tristate all outputs
0 1 0
Note 1: Default at power-up will be for latched logic inputs to define frequency, as displayed byBit 3.
4
ICS9248-107
Byte 1: CPU, Active/Inactive Register (1 = enable, 0 = disable)
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # 40 38 37 42 47 46 44 PWD 1 1 1 1 1 1 1 X Description CPUCLK 1 CPUCLK 2 CPUCLK 3 CPUCLK 0 IOAPIC0 IOAPIC1 IOAPIC2 (Reserved)
Byte 2: PCI Active/Inactive Register (1 = enable, 0 = disable)
Bit Pin # PWD Description
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
18 17 15 14 12 11 9 8
1 1 1 1 1 1 1 1
PCICLK7 PCICLK6 PCICLK5 PCICLK4 PCICLK3 PCICLK2 PCICLK1 PCICLK_F
Notes: 1. Inactive means outputs are held LOW and are disabled from switching.
Notes: 1. Inactive means outputs are held LOW and are disabled from switching.
Byte 3: 3V66 Active/Inactive Register (1 = enable, 0 = disable)
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # 34 33 32 2 3 PWD 1 1 1 X 1 1 X X Description 3V66_0 3V66_1 3V66_2 FS1# REF0 REF1 FS3# FS2#
Byte 4: PCI Active/Inactive Register (1 = enable, 0 = disable)
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # 26 27 22 21 20 PWD 1 1 X 1 1 1 1 X Description 24_48MHz 48MHz FS0# (Reserved) PCICLK10 PCICLK9 PCICLK8 FS4#
Notes: 1. Inactive means outputs are held LOW and are disabled from switching.
Notes: 1. Inactive means outputs are held LOW and are disabled from switching.
Byte 5: Active/Inactive Register (1= enable, 0 = disable)
Bit Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Pin # PWD 1 1 1 1 1 1 1 1 Description R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e )
Byte6: Active/Inactive Register (1= enable, 0 = disable)
Bit Pin # PWD Description
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
-
0 0 0 0 0 1 1 0
R e s e r ve d R e s e r ve d R e s e r ve d R e s e r ve d R e s e r ve d R e s e r ve d R e s e r ve d R e s e r ve d
(Note) (Note) (Note) (Note) (Note) (Note) (Note) (Note)
Notes: 1. Inactive means outputs are held LOW and are disabled from switching.
Note: Don't write into this register, writing into this register can cause malfunction
5
ICS9248-107
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ambient Operating Temperature . . . . . . . . . . . . Storage Temperature . . . . . . . . . . . . . . . . . . . . . . Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V GND -0.5 V to VDD +0.5 V 0C to +70C -65C to +150C 115C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5% (unless otherwise stated) PARAMETER SYMBOL CONDITIONS Input High Voltage VIH Input Low Voltage VIL VIN = VDD Input High Current IIH VIN = 0V; Inputs with no pull-up resistors Input Low Current IIL1 VIN = 0V; Inputs with pull-up resistors Input Low Current IIL2 IDD3.3OP100 CL = 0 pF; Select @ 100 MHz Operating Supply Current IDD3.3OP133 CL = 0 pF; Select @ 133 MHz IDD3.3PD CL = 0 pF; PWRDWN#=0 Powerdown Current VDD = 3.3 V Input Frequency Fi Logic Inputs CIN 1 Input Capacitance X1 & X2 pins CINX Transition time
1 1
MIN 2 VSS-0.3 -5 -200
11 27
MAX UNITS VDD+0.3 V 0.8 V 5 A A A 160 mA 160 mA A 600 14.318 16 MHz 5 pF 45 pF 3 3 3 ms ms ms
TYP
Ttrans Ts TSTAB
To 1st crossing of target frequency From 1st crossing to 1 % target frequency. From VDD = 3.3 V to 1% target frequency
Settling Time 1 Clk Stabilization
1
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; VDD = 3.3 V +/- 5%, VDDL = 2.5V +/- 5% (unless otherwise stated). PARAMETER SYMBOL CONDITIONS IDD2.5OP100 CL = 0 pF; Select @ 100 MHz Operating Supply Current IDD2.5OP133 CL = 0 pF; Select @ 133 MHz IDD2.5PD CL = 0 pF; PWRDWN# = 0 Power Down Supply Current MIN TYP MAX 75 90 100 UNITS mA mA A
6
ICS9248-107
Electrical Characteristics - Group Offset
TA = 0 - 70C; VDD = 3.3 V +/- 5%, VDDL = 2.5V +/- 5% (unless otherwise stated). Group Offset Measurement Loads CPU to 3V66 0.8 to 1.8 ns CPU leads CPU @ 20 pF, 3V66 @ 30 pF CPU to PCI 0 to 1.5 ns CPU leads CPU @ 20 pF, PCI @ 30 pF 1.5 to 4.0 ns CPU leads CPU @ 20 pF, IOAPIC @ 20 pF CPU to IOAPIC Measurement Points CPU @ 1.25V, 3V66 @ 1.5 V CPU @ 1.25V, PCI @ 1.5 V CPU @ 1.25V, IOAPIC @ 1.25 V
Electrical Characteristics - CPUCLK
TA = 0 - 70 C; VDD = 3.3 V +/-5%, VDDL = 2.5V +/- 5 %; CL = 20 pF (unless otherwise stated). PARAMETER SYMBOL CONDITIONS MIN Output High Voltage VOH2B IOH = -12 mA 2 IOL = 12 mA Output Low Voltage VOL2B IOH2B VOH = 1.7 V Output High Current IOL2B VOL = 0.7 V 19 Output Low Current 1 Rise Time tr2B VOL = 0.4 V, VOH = 2.0 V 0.4 1 Fall Time tf2B VOH = 2.0 V, VOL = 0.4 V 0.4 1 dt2B VT = 1.25 V CPU frequency < 142 MHz 45 Duty Cycle 1 dt2B VT = 1.25 V CPU frequency > 142 MHz 42 1 Skew tsk2B VT = 1.25 V 1 tjcyc-cyc2B VT = 1.25 V Jitter, Cycle-to-cycle
1
TYP 2.3 0.3 -35 26 1.03 1.11 49.3 46.4 75 141
MAX UNITS V 0.4 V -19 mA mA 1.6 ns 1.6 ns 55 % 52 % 175 ps 250 ps
Guaranteed by design, not 100% tested in production.
7
ICS9248-107
Electrical Characteristics - 3V66
TA = 0 - 70 C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 30 pF (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN IOH = -25 mA 2.4 Output High Voltage VOH1 Output Low Voltage VOL1 IOL = 20 mA Output High Current IOH1 VOH = 2.0 V Output Low Current IOL1 VOL = 0.8 V 41 VOL = 0.4 V, VOH = 2.4 V 0.5 Rise Time Tr1 VOH = 2.4 V, VOL = 0.4 V 0.5 Fall Time Tf1 1 VT = 1.5 V 45 Duty Cycle Dt Skew Jitter, Cycle-to-cycle
1
TYP 2.9 0.32 -73 50 1.41 1.41 50.1 86 162
MAX UNITS V 0.4 V -40 mA mA 2 ns 2 ns 55 % 250 500 ps ps
Tsk11 tjcyc-cyc11
VT = 1.5 V VT = 1.5 V
Guarenteed by design, not 100% tested in production.
Electrical Characteristics - PCICLK
TA = 0 - 70 C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 30 pF (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN Output High Voltage VOH1 IOH = -11 mA 2.4 IOL = 9.4 mA Output Low Voltage VOL1 VOH = 2.0 V Output High Current IOH1 VOL = 0.8 V 25 Output Low Current IOL1 Rise Time1 Fall Time
1 1
TYP 3.1 0.17 -62 45 1.75 1.58 50.3 274 96 496 133
MAX UNITS V 0.4 V -22 mA mA 2.5 2.5 55 400 250 580 500 ns ns % ps ps ps ps
tr1 tf1 dt1 tsk1 tsk1 tsk1 tjcyc-cyc1
VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V, PCICLK (F:7) VT = 1.5 V, PCICLK (8:10) VT = 1.5 V, PCICLK (F:10) VT = 1.5 V
0.5 0.5 45
Duty Cycle Skew1
Jitter, Cycle-to-cycle
1
1
Guaranteed by design, not 100% tested in production.
8
ICS9248-107
Electrical Characteristics - 24MHz, 48MHz
TA = 0 - 70 C; VDD = 3.3 V +/- 5%, VDDL = 2.5 V +/- 5 %; CL = 20 pF (unless otherwise stated). PARAMETER SYMBOL CONDITIONS Output High Voltage VOH5 IOH = -12 mA IOL = 9 mA Output Low Voltage VOL5 IOH5 VOH = 2.0 V Output High Current IOL5 VOL = 0.8 V Output Low Current 1 Rise Time tr5 VOL = 0.4 V, VOH = 2.4 V VOH = 2.4V, VOL = 0.4 V Fall Time tf51 Duty Cycle dt51 VT = 1.5 V VT = 1.5 V tjcyc-cyc51 Jitter, Cycle-to-Cycle
1
MIN 2.6
16
45
TYP 2.9 0.3 -27 22 2.05 2.13 50.7 314
MAX UNITS V 0.4 V -22 mA mA 4 ns 4 ns 55 % 500 ps
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - REF
TA = 0 - 70 C; VDD = 3.3 V +/- 5%, VDDL = 2.5 V +/- 5 %; CL = 20 pF (unless otherwise stated). PARAMETER SYMBOL CONDITIONS Output High Voltage VOH5 IOH = -12 mA Output Low Voltage VOL5 IOL = 9 mA IOH5 VOH = 2.0 V Output High Current IOL5 VOL = 0.8 V Output Low Current Rise Time tr51 VOL = 0.4 V, VOH = 2.4 V Fall Time tf51 VOH = 2.4V, VOL = 0.4 V Duty Cycle dt51 VT = 1.5 V 1 VT = 1.5 V tjcyc-cyc5 Jitter, Cycle-to-Cycle
1
MIN 2.6
16
45
TYP 2.9 0.3 -27 22 1.97 2.10 52.5 590
MAX UNITS V 0.4 V -22 mA mA 4 ns 4 ns 55 % 1000 ps
Guaranteed by design, not 100% tested in production.
9
ICS9248-107
Electrical Characteristics - IOAPIC
TA = 0 - 70 C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 20 pF (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN Output High Voltage VOH4B IOH = -12.0 mA 2 IOL = 12 mA Output Low Voltage VOL4B VOH = 1.7 V Output High Current IOH4B Output Low Current IOL4B VOL = 0.7 V 19 1 VOL = 0.4 V, VOH = 2.0 V 0.5 Rise Time tr4B VOH = 2.0 V, VOL = 0.4 V 0.5 Fall Time tf4B1 1 VT = 1.25 V 45 Duty Cycle dt4B 1 tsk4B VT = 1.25 V Skew tjcyc-cyc4B1 VT = 1.25 V Jitter, Cycle-to-cycle
1
TYP 2.3 0.31 -33 27 1.65 1.66 49.4 95 120
MAX UNITS V 0.4 V -19 mA mA 2 ns 2 ns 55 % 250 500 ps
Guaranteed by design, not 100% tested in production.
10
ICS9248-107
Power Management Features:
PD# 0 1 CPUCLK IOAPIC LOW ON LOW ON 3V66 LOW ON PCI LOW ON PCI_F LOW ON REF. 48MHz LOW ON Osc OF F ON VCOs OFF ON
Note: 1. LOW means outputs held static LOW as per latency requirement next page. 2. On means active. 3. PD# pulled Low, impacts all outputs including REF and 48 MHz outputs.
Power Management Requirements:
Latency Signal Signal State 1 (normal operation) 0 (power down) No. of rising edges of PCICLK 3mS 2max.
PD#
Note: 1. Clock on/off latency is defined in the number of rising edges of free running PCICLKs between the clock disable goes low/ high to the first valid clock comes out of the device. 2. Power up latency is when PWR_DWN# goes inactive (high) to when the first valid clocks are dirven from the device.
11
ICS9248-107
General I2C serial interface information
The information in this section assumes familiarity with I2C programming. For more information, contact ICS for an I2C programming application note.
How to Write:
Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends a dummy command code ICS clock will acknowledge Controller (host) sends a dummy byte count ICS clock will acknowledge Controller (host) starts sending first byte (Byte 0) through byte 6 * ICS clock will acknowledge each byte one at a time. * Controller (host) sends a Stop bit
How to Write:
Controller (Host) Start Bit Address D2(H) Dummy Command Code ACK Dummy Byte Count ACK Byte 0 ACK Byte 1 ACK Byte 2 ACK Byte 3 ACK Byte 4 ACK Byte 5 ACK Byte 6 ACK Stop Bit ICS (Slave/Receiver)
How to Read:
* * * * * * * * Controller (host) will send start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the byte count Controller (host) acknowledges ICS clock sends first byte (Byte 0) through byte 6 Controller (host) will need to acknowledge each byte Controller (host) will send a stop bit
* * * * * * * *
How to Read:
Controller (Host) Start Bit Address D3(H) ICS (Slave/Receiver)
ACK
ACK Byte Count ACK Byte 0 ACK Byte 1 ACK Byte 2 ACK Byte 3 ACK Byte 4 ACK Byte 5 ACK Byte 6 ACK Stop Bit
Notes:
1. 2. 3. 4. 5. The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for verification. Read-Back will support Intel PIIX4 "Block-Read" protocol. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode) The input is operating at 3.3V logic levels. The data byte format is 8 bit bytes. To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued. At power-on, all registers are set to a default condition, as shown.
6.
12
ICS9248-107
PD# Timing Diagram
The power down selection is used to put the part into a very low power state without turning off the power to the part. PD# is an asynchronous active low input. This signal needs to be synchronized internal to the device prior to powering down the clock synthesizer. Internal clocks are not running after the device is put in power down. When PD# is active low all clocks need to be driven to a low value and held prior to turning off the VCOs and crystal. The power up latency needs to be less than 3 mS. The power down latency should be as short as possible but conforming to the sequence requirements shown below. The REF and 48MHz clocks are expected to be stopped in the LOW state as soon as possible. Due to the state of the internal logic, stopping and holding the REF clock outputs in the LOW state may require more than one clock cycle to complete.
PD#
CPUCLK 3V66 PCICLK VCO Crystal
Notes: 1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248 device). 2. As shown, the outputs Stop Low on the next falling edge after PD# goes low. 3. PD# is an asynchronous input and metastable conditions may exist. This signal is synchronized inside this part. 4. The shaded sections on the VCO and the Crystal signals indicate an active clock. 5. Diagrams shown with respect to 133MHz. Similar operation when CPU is 100MHz.
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ICS9248-107
N
c
L
SYMBOL A A1 b c D E E1 e h L N
INDEX AREA
E1
E
12 D h x 45
a
A A1
In Millimeters COMMON DIMENSIONS MIN MAX 2.41 2.80 0.20 0.40 0.20 0.34 0.13 0.25 SEE VARIATIONS 10.03 10.68 7.40 7.60 0.635 BASIC 0.38 0.64 0.50 1.02 SEE VARIATIONS 0 8 VARIATIONS D mm. MIN MAX 15.75 16.00
In Inches COMMON DIMENSIONS MIN MAX .095 .110 .008 .016 .008 .0135 .005 .010 SEE VARIATIONS .395 .420 .291 .299 0.025 BASIC .015 .025 .020 .040 SEE VARIATIONS 0 8
-Ce
b SEATING PLANE .10 (.004) C
N 48
10-0034
D (inch) MIN .620 MAX .630
Reference Doc.: JEDEC Publication 95, MO-118
300 mil SSOP Package
Ordering Information
ICS9248yF-107
Example:
ICS XXXX y F - PPP
Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type F=SSOP
Revision Designator
Device Type Prefix ICS, AV = Standard Device
14
ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.

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